Figure 8.1 Block Diagram Of Rfu - Renesas H8S/2158 User Manual

Section 8 RAM-FIFO Unit (RFU)
Internal address bus
Legend:
BAR : Base address register
RAR : Read address pointer
TMP : Temporary pointer
WAR : Write address pointer
DATAN : Valid data byte number
FREEN : Free area byte number
NRA : Read start address
NWA : Write start address
DTCRA : Data transfer control register A
DTCRB : Data transfer control register B
Notes: * Pointer sets 1 to 3 have a function similar to pointer set 0.
Rev. 3.00 Jan 25, 2006 page 168 of 872
REJ09B0286-0300
Internal data bus
Internal data bus interface
Pointer set 0
BAR_0
RAR_0
TMP_0
WAR_0
DTCRA_0
DTCRB_0
DTSTRC_0
DTIDR_0
Pointer set 1*
Pointer set 2*
Pointer set 3*
DATAN/FREEN
NRA/NWA
DTCRC
DTCRD
DTSTRA
DTSTRB
DTIER
DTRSR
DTIDSRA
DTIDSRB
DTSTRC : Data transfer status register C
DTIDR : Data transfer ID register
DTIDSRA : Data transfer ID read/write select register A
DTIDSRB : Data transfer ID read/write select register B
DTSTRA : Data transfer status register A
DTSTRB : Data transfer status register B
DTCRC : Data transfer control register C
DTCRD : Data transfer control register D
DTIER : Data transfer interrupt enable register
DTRSR : Data transfer register select register

Figure 8.1 Block Diagram of RFU

RFU activation request
DTI0 to DTI3
DTIE
Interrupt signal