Renesas H8S/2158 User Manual page 563

Bit Bit Name Initial Value
7 CNTE 0
6 STOPIMX 0
5 CNTS1 0
4 CNTS0 0
3 BBC3 1
2 BBC2 1
1 BBC1 1
0 BBC0 1
R/W Description
R/W Timeout Counter Enable
Starts or stops the timeout counter.
0: Stops the timeout counter and clears the internal
counter
1: Operates the timeout counter
R/W Stop Condition Interrupt Source Mask X
Selects whether to enable CREQ interrupt requests
by stop conditions.
0: CREQ interrupt requests by stop conditions are
enabled
1: CREQ interrupt requests by stop conditions are
disabled
R/W Counter Select
R/W These bits specify the number of clock cycles for the
timeout counter. The clock is selected by the IICX1
and IICX0 bits in STCR and the CKS2 to CKS0 bits
in ICMR.
00: 32 clock cycles
01: 34 clock cycles
10: 128 clock cycles
11: 256 clock cycles
R Frame Bit Count
R These bits count the frame bit at each rising edge of
SCL. These bits are cleared to B'0000 at the first
R
rising edge, and are incremented by 1 at each rising
R
edge. After being incremented to B'0111 at the eighth
rising edge, these bits are initialized to B'1111 at the
next rising edge (for acknowledge).
Rev. 3.00 Jan 25, 2006 page 509 of 872
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Section 17 I C Bus Interface (IIC)
REJ09B0286-0300