Suspend/Resume Operation; Usb Module Reset And Operation Stop Modes - Renesas H8S/2158 User Manual

16-bit single-chip microcomputer h8s family/h8s/2100 series
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Section 18 Universal Serial Bus Interface (USB)
18.4.5

Suspend/Resume Operation

The USB function core automatically enters a suspend state if the USB data line is placed in an
idle state for a time equal to or greater than that specified by the USB standard Rev. 1.1.
A suspend state is automatically cancelled (resumed) when the upstream (host) resumes data
transfer. A suspend state can also be forcibly cancelled (resumed) by the USB function (remote
wakeup).
Suspend state and resume state transitions can be detected by the SPNDIF and SPNDOF flags. A
SPNDOF interrupt can be accepted by waking up this LSI even if the LSI is placed in software
standby mode. In this case, the oscillator and PLL circuit must be started up according to the
startup sequence.
Whether remote wakeup is enabled or not is checked by the RWUPS flag of DEVRSMR. If
remote wakeup is enabled, remote wakeup is performed by setting the DVR bit of DEVRSMR
to 1.
18.4.6

USB Module Reset and Operation Stop Modes

The USB module can be placed in a reset state or operation stop mode by using multiple control
bits. To startup the USB module by sequentially specifying these control bits, refer to section
18.4.7, USB Module Startup Sequence.
The USB supports the following reset and operating stop states. Hardware standby and reset states
initializes the entire USB module. In each register description, initialization conditions are not
described and only initial values are shown.
1. Hardware standby mode
2. Reset state
3. Module stop mode
4. Software standby mode
5. USB bus reset state
6. USB suspend state
Hardware Standby Mode: Hardware standby mode is entered by bringing the STBY pin of the
LSI to low. In hardware standby mode, registers that can be initialized and the internal status of
the LSI are initialized and all pins of the LSI are placed in a high impedance state.
XTAL-EXTAL system clock oscillation stops in the clock pulse generator.
Rev. 3.00 Jan 25, 2006 page 618 of 872
REJ09B0286-0300

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