Transmission/Reception Of Consecutive Data Blocks; Table 8.6 Settings When Using Boundary Overflow (Transmission/Reception Of Single Data Block) - Renesas H8S/2158 User Manual

Section 8 RAM-FIFO Unit (RFU)
Table 8.6 Settings when Using Boundary Overflow (Transmission/Reception of Single
Data Block)
Transfer Condition
Number of transfer data bytes
FIFO size
Base address
Read pointer
Write pointer
When the number of transfer data bytes has been transmitted from RAM to the peripheral modules
the read pointer becomes 0, and boundary overflow occurs. At this time, the BOVF_R flag in
DTSTRC is set to 1.
When the number of transfer data bytes has been received from the peripheral modules to RAM,
the write pointer becomes 0, and boundary overflow occurs. At this time, the BOVF_W flag in
DTSTRC is set to 1.
8.8.2

Transmission/Reception of Consecutive Data Blocks

If the peripheral module includes a function to generate an interrupt request at the completion of
the specified number of bytes of transfer data, data blocks can be processed consecutively
according to the following procedure. An example in which the ID to be written to the RFU is
enabled and receive data is processed by the CPU is shown below.
1. The pointer set is initialized.
2. ID of RFU write is enabled.
3. Data transfer of the corresponding peripheral module is initiated.
4. Data block receive end interrupt (peripheral module).
5. RAR and DATAN are read from, and receive data block processing is started by the CPU.
When FIFO has sufficient free area after starting the CPU processing at the 5th step, the next
block transfer can be started, returning to the 3rd step.
At this time, the RFU is the FIFO-size ring buffer, specified by bits BUD2 to BUD0 in DTCRA. If
the contents of the RFU pointer exceed the FIFO size, it automatically becomes the remainder of
Rev. 3.00 Jan 25, 2006 page 192 of 872
REJ09B0286-0300
RAM → → → → Peripheral
Modules
— N_R
BUD2 to BUD0 Sz
BAR Clear the bits lower
than the boundary to
0 according to the
FIFO size.
RAR Sz – N_R
WAR 0
Peripheral Modules
→ → → → RAM
N_W
Sz
Clear the bits lower
than the boundary to
0 according to the
FIFO size.
Sz – N_W
Sz – N_W