Timing Of On-Chip Peripheral Modules; Figure 29.14 Burst Rom Access Timing/1-State Access - Renesas H8S/2158 User Manual

φ
A17 to A0, IOS * ,
CS256, CPCS1
AS *
RD
(Read)
D15 to D0
(Read)
Note: * AS is multiplexed with IOS. Either the AS or IOS function can be selected by the IOSE bit of SYSCR.

Figure 29.14 Burst ROM Access Timing/1-State Access

29.3.4

Timing of On-Chip Peripheral Modules

Tables 29.10 to 29.14 show the on-chip peripheral module timing. The on-chip peripheral modules
that can be operated by the subclock (φ = 32.768 kHz) are I/O ports, external interrupts (NMI,
IRQ15 to IRQ0, KIN9 to KIN0, and WUE15 to WUE8), watchdog timer, and 8-bit timer
(channels 0 and 1) only.
T 1 T 2 or T 3
Section 29 Electrical Characteristics
T 1
t
AD
t t t
ACC1 RDS RDH
Rev. 3.00 Jan 25, 2006 page 845 of 872
t
RSD2
REJ09B0286-0300