Figure 16.2 Block Diagram Of Sci_0 And Sci_2 - Renesas H8S/2158 User Manual

Section 16 Serial Communication Interface (SCI, IrDA, and CRC)
RDR
RxD0/
RSR
RxD2
TxD0/
TxD2
Parity check
SSE0I/
SSE2I
SCK0/
SCK2
Legend:
: Receive shift register
RSR
: Receive data register
RDR
: Transmit shift register
TSR
: Transmit data register
TDR
: Serial mode register
SMR
Rev. 3.00 Jan 25, 2006 page 390 of 872
REJ09B0286-0300
Module data bus
TDR
TSR
Transmission/
reception control
Parity generation
C/A
CKE1
SSE
: Serial control register
SCR
: Serial status register
SSR
: Smart card mode register
SCMR
: Bit rate register
BRR
: Serial enhanced mode register
SEMR
: Serial RFU enable register
SCIDTER

Figure 16.2 Block Diagram of SCI_0 and SCI_2

SCMR
BRR
SSR
SCR
Baud rate
SMR
generator
SEMR
SCIDTER
Clock
Average transfer
rate generator
At 10.667-MHz
operation
Extenal clock
• 115.152 kbps
• 460.606 kbps
At 16-MHz operation
• 115.196 kbps
• 230.392 kbps
• 460.784 kbps
• 720kbps
At 20-MHz operation
• 115.196 kbps
• 230.392 kbps
At 24-MHz operation
• 115.196 kbps
• 230.392 kbps
• 460.784 kbps
• 720 kbps
φ
φ/4
φ/16
φ/64
TEI
TXI
RXI
ERI
RFU activation request