Normal Mode; I/O Select Signals; Figure 6.2 Ios Signal Output Timing; Table 6.8 Address Range For Ios Signal Output - Renesas H8S/2158 User Manual

Section 6 Bus Controller
6.4.3

Normal Mode

The external address space is initialized as the basic bus interface and a 3-state access space. In
mode 3 (normal mode), the address space other than on-chip ROM, on-chip RAM, internal I/O
registers, and their reserved areas is specified as the external address space. The on-chip RAM
area is enabled when the RAME bit in SYSCR is set to 1, and disabled and specified as the
external address space when the RAME bit is cleared to 0.
6.4.4

I/O Select Signals

The LSI can output I/O select signals (IOS); the signal is driven low when the corresponding
external address space is accessed. Figure 6.2 shows an example of IOS signal output timing.
Address bus
Enabling or disabling IOS signal output is performed by the IOSE bit in SYSCR. In extended
mode, the IOS pin functions as an AS pin by a reset. To use this pin as an IOS pin, set the IOSE
bit to 1. For details, refer to section 9, I/O Ports.
The address ranges of the IOS signal output can be specified by the IOS1 and IOS0 bits in BCR,
as shown in table 6.8.
Address Range for IOS
Table 6.8
IOS1 IOS0
0 0
1
1 0
1
Rev. 3.00 Jan 25, 2006 page 122 of 872
REJ09B0286-0300
T
1
φ
IOS
Figure 6.2 IOS IOS Signal Output Timing
IOS IOS
IOS Signal Output
IOS IOS
IOS IOS Signal Output Range
IOS IOS
H'(FF)F000 to H'(FF)F03F
H'(FF)F000 to H'(FF)F0FF
H'(FF)F000 to H'(FF)F3FF
H'(FF)F000 to H'(FF)F7FF
Bus cycle
T
2
External addresses selected by IOS
T
3
(Initial value)