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6.7.3
Basic Operation Timing ....................................................................................... 138
6.7.4
Wait Control ........................................................................................................ 140
6.8
Idle Cycle .......................................................................................................................... 141
6.9
Bus Arbitration.................................................................................................................. 142
6.9.1
Bus Master Priority .............................................................................................. 142
6.9.2
Bus Transfer Timing ............................................................................................ 143
7.1
Features ............................................................................................................................. 145
7.2
Register Descriptions ........................................................................................................ 146
7.2.1
DTC Mode Register A (MRA) ............................................................................ 147
7.2.2
DTC Mode Register B (MRB)............................................................................. 148
7.2.3
DTC Source Address Register (SAR).................................................................. 149
7.2.4
DTC Destination Address Register (DAR).......................................................... 149
7.2.5
DTC Transfer Count Register A (CRA) .............................................................. 149
7.2.6
DTC Transfer Count Register B (CRB)............................................................... 149
7.2.7
DTC Enable Registers (DTCER) ......................................................................... 150
7.2.8
DTC Vector Register (DTVECR)........................................................................ 151
7.3
Activation Sources ............................................................................................................ 152
7.4
Location of Register Information and DTC Vector Table ................................................ 153
7.5
Operation........................................................................................................................... 156
7.5.1
Normal Mode....................................................................................................... 157
7.5.2
Repeat Mode ........................................................................................................ 158
7.5.3
Block Transfer Mode ........................................................................................... 159
7.5.4
Chain Transfer ..................................................................................................... 160
7.5.5
Interrupts.............................................................................................................. 161
7.5.6
Operation Timing................................................................................................. 161
7.5.7
Number of DTC Execution States........................................................................ 163
7.6
Procedures for Using DTC................................................................................................ 164
7.6.1
Activation by Interrupt......................................................................................... 164
7.6.2
Activation by Software ........................................................................................ 164
7.7
Examples of Use of the DTC ............................................................................................ 164
7.7.1
Normal Mode....................................................................................................... 164
7.7.2
Software Activation ............................................................................................. 165
7.8
Usage Notes ...................................................................................................................... 166
7.8.1
Module Stop Mode Setting .................................................................................. 166
7.8.2
On-Chip RAM ..................................................................................................... 166
7.8.3
DTCE Bit Setting................................................................................................. 166
7.8.4
Setting Required on Entering Subactive Mode or Watch Mode .......................... 166
7.8.5
DTC Activation by Interrupt Sources of SCI, IIC, or A/D Converter.................. 166
7.8.6
DTC Activation by Interrupt Sources of USB or MCIF ...................................... 166
Rev. 3.00 Jan 25, 2006 page xx of lii
................................................................... 145
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