Timing Of On-Chip Peripheral Modules; Table 21.6 Timing Of On-Chip Peripheral Modules (1) - Renesas H8SX/1520 Series Hardware Manual

Section 21 Electrical Characteristics
Iφ
21.3.3

Timing of On-Chip Peripheral Modules

Table 21.6 Timing of On-Chip Peripheral Modules (1)

Conditions: V
V
T
I/O ports Output data delay time
Input data setup time
Input data hold time
Realtime input port data hold
time
TPU Timer output delay time
Timer input setup time
Timer clock input setup time
Timer clock
pulse width
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NMI
IRQi*
(i = 0 to 14)
IRQ*
(edge input)
IRQ*
(level input)
Note: * SSIER must be set to cancel software standby mode.
Figure 21.7 Interrupt Input Timing
= 4.5 V to 5.5 V, AV
CC
= AV = 0 V, Pφ = 8 to 35 MHz,
SS SS
= –40°C to +85°C (wide-range specifications)
a
Item
Single-edge
setting
Both-edge
setting
t t
NMIS NMIH
t
NMIW
t
IRQW
t t
IRQS IRQH
t
IRQS
= 4.5 V to 5.5 V, AV
CC0
Symbol Min.

t
PWD
t 25
PRS
t 25
PRH
t 4
RTIPH

t
TOCD
t 25
TICS
t 25
TCKS
t 1.5
TCKWH
t 2.5
TCKWL
= 4.5 V to 5.5 V,
CC1
Max. Unit Test Conditions
40 ns Figure 21.8

ns

ns

t Figure 21.9
cyc
40 ns Figure 21.10

ns

ns Figure 21.11

t
cyc

t
cyc