Timer Control Register (Tcr) - Renesas H8S/2158 User Manual

13.3.4

Timer Control Register (TCR)

TCR selects the TCNT clock source and the condition by which TCNT is cleared, and
enables/disables interrupt requests.
Bit Bit Name Initial Value R/W
7 CMIEB 0
6 CMIEA 0
5 OVIE 0
4 CCLR1 0
3 CCLR0 0
2 CKS2 0
1 CKS1 0
0 CKS0 0
Description
R/W Compare-Match Interrupt Enable B
Selects whether the CMFB interrupt request (CMIB) is
enabled or disabled when the CMFB flag in TCSR is set
to 1.
0: CMFB interrupt request (CMIB) is disabled
1: CMFB interrupt request (CMIB) is enabled
R/W Compare-Match Interrupt Enable A
Selects whether the CMFA interrupt request (CMIA) is
enabled or disabled when the CMFA flag in TCSR is set
to 1.
0: CMFA interrupt request (CMIA) is disabled
1: CMFA interrupt request (CMIA) is enabled
R/W Timer Overflow Interrupt Enable
Selects whether the OVF interrupt request (OVI) is
enabled or disabled when the OVF flag in TCSR is set
to 1.
0: OVF interrupt request (OVI) is disabled
1: OVF interrupt request (OVI) is enabled
R/W Counter Clear 1, 0
R/W These bits select the method by which the timer counter
is cleared.
00: Clearing is disabled
01: Cleared on compare-match A
10: Cleared on compare-match B
11: Cleared on rising edge of external reset input
R/W Clock Select 2 to 0
R/W These bits select the clock input to TCNT and count
condition, together with the ICKS1 and ICKS0 bits in
R/W
STCR. For details, see table 13.2.
Section 13 8-Bit Timer (TMR)
Rev. 3.00 Jan 25, 2006 page 321 of 872
REJ09B0286-0300