Bus Timing; Table 29.9 Bus Timing (1) (Normal Mode And Advanced Mode) - Renesas H8S/2158 User Manual

29.3.3

Bus Timing

Table 29.9 shows the bus timing. In subclock (φ = 32.768 kHz) operation, external expansion
mode operation cannot be guaranteed.

Table 29.9 Bus Timing (1) (Normal Mode and Advanced Mode)

Condition A: V = 3.0 V to 3.6 V, V
CC
Condition B: V = 2.7 V to 3.6 V, V
CC
Item Symbol
Address delay time t
Address setup time t
Address hold time t
CS delay time (IOS,
t
CS256, CPCS1,
CPCS2)
AS delay time
t
RD delay time 1
t
RD delay time 2
t
Read data setup time t
Read data hold time t
Read data access t
time 1
Read data access t
time 2
Read data access t
time 3
t
Read data access
time 4
Read data access t
time 5
WR delay time 1
t
WR delay time 2
t
WR pulse width 1
t
WR pulse width 2
t
Write data delay time t
Write data setup time t
Write data hold time t
WAIT setup time
t
WAIT hold time
t
= 0 V, φ = 5 MHz to 25 MHz
SS
= 0 V, φ = 5 MHz to 20 MHz
SS
Condition A
Min
—
AD
0.5 × t
–15
AS cyc
0.5 × t
– 10
AH cyc
—
CSD
—
ASD
—
RSD1
—
RSD2
15
RDS
0
RDH
—
ACC1
—
ACC2
—
ACC3
—
ACC4
—
ACC5
—
WRD1
—
WRD2
1.0 × t
– 20
WSW1 cyc
1.5 × t
– 20
WSW2 cyc
—
WDD
0
WDS
10
WDH
25
WTS
5
WTH
Section 29 Electrical Characteristics
Condition B
Max Min
—
20
— 0.5 × t
cyc
—
0.5 × t
cyc
—
15
—
15
—
15
—
15
—
15
—
0
1.0 × t —
–
cyc
30
1.5 × t —
–
cyc
25
—
2.0 × t
–
cyc
30
—
2.5 × t
–
cyc
25
3.0 × t —
–
cyc
30
—
15
—
15
— 1.0 × t
cyc
— 1.5 × t
cyc
—
30
—
0
—
10
—
25
—
5
Rev. 3.00 Jan 25, 2006 page 839 of 872
Max Unit
25 ns
—
– 15
—
– 10
15
15
15
15
—
—
1.0 × t
– 35
cyc
1.5 × t
– 30
cyc
2.0 × t
– 35
cyc
2.5 × t
– 30
cyc
3.0 × t
– 35
cyc
15
15
—
– 20
—
– 20
35
—
—
—
—
REJ09B0286-0300
Test
Conditions
Figures
29.9 to
29.14