Table 17.5 Restrictions On Accessing Iic Registers - Renesas H8S/2158 User Manual

Table 17.5 Restrictions on Accessing IIC Registers

Register Bit Bit Name
ICDR 7 to 0 —
SAR 7 to 1 SVA6 to SVA0
0 FS
SARX 7 to 1 SVAX6 to SVAX0
0 FSX
ICMR 7 MLS
6 WAIT
5 to 3 CKS2 to CKS0
2 to 0 BC2 to BC0
ICCR 7 ICE
6 IEIC
5 MST
4 TRS
3 ACKE
2 BBSY
1 IRIC
0 SCP
ICSR 7 ESTP
6 STOP
5 IRTR
4 AASX
3 AL
2 AAS
1 ADZ
0 ACKB
R/W Description
R/W Writing is disabled. Reading/writing to this
register does not initiate any data transfer.
Writing has no affect on the bits.
R/W Write the slave address.
2
R/W Select the I C bus format.
R/W Write the second slave address as required.
2
R/W Select the I C bus format.
R/W Select MSB-first.
R/W The value written to this bit is ignored because
the function of this bit is replaced by ICCMD.
The function of this bit can be monitored by the
WAITX bit in ICSRA.
R/W Select the transfer rate.
R/W Set to B'000 (9 bits).
R/W —
R/W Even when set to 1, the conventional interrupt
is ignored.
R/W The values written to these bits are ignored
because the functions of these bits are
R/W
replaced by ICCMD. The functions of these bits
R/W
can be monitored by the MSTX, TRSX, and
ACKXE bits in ICSRA.
R/W Writing B'10 or B'00 is ignored.
R/W —
W Writing B'10 or B'00 is ignored.
R/(W) —
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R/W The value written to this bit is ignored because
the function of this bit when written to is
replaced by the ACKXB bit in ICCRX.
Rev. 3.00 Jan 25, 2006 page 511 of 872
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Section 17 I C Bus Interface (IIC)
REJ09B0286-0300