Figure 26.5 External Clock Input Timing; Table 26.3 External Clock Input Conditions - Renesas H8S/2158 User Manual

Section 26 Clock Pulse Generator

Table 26.3 External Clock Input Conditions

Item
External clock
input pulse width
low level
External clock
input pulse width
high level
External clock
rising time
External clock
falling time
Clock pulse width
low level
Clock pulse width
high level
EXTAL
The oscillator and duty correction circuit have a function to adjust the waveform of the external
clock input that is input to the EXTAL pin. When a specified clock signal is input to the EXTAL
pin, internal clock signal output is determined after the external clock output stabilization delay
time (t ) has passed. As the clock signal output is not determined during the t
DEXT
signal should be set to low to hold it in reset state. Table 26.4 shows the external clock output
stabilization delay time. Figure 26.6 shows the timing of the external clock output stabilization
delay time.
Rev. 3.00 Jan 25, 2006 page 764 of 872
REJ09B0286-0300
VCC = 3.0 to 3.6 V
Symbol Min
t 15
EXL
t 15
EXH
t —
EXr
t —
EXf
t 0.4
CL
t 0.4
CH
t
EXH
t
EXr

Figure 26.5 External Clock Input Timing

VCC = 2.7 to 3.6 V
Max Min
— 20
— 20
5 —
5 —
0.6 0.4
0.6 0.4
t
EXL
t
EXf
Test
Max Unit Conditions
— ns Figure 26.5
— ns
5 ns
5 ns
0.6 t Figure 29.4
cyc
0.6 t
cyc
V × 0.5
CC
cycle, a reset
DEXT