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Operating
Mode
MST
TRS
BBSY ESTP STOP IRTR
Slave
0
1
1
mode
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0↓
Legend:
0:
Retains 0
1:
Retains 1
: Retains the previous state
0↓: Cleared to 0
1↑: Set to 1
Notes:
1. Set to 1 when 1 is received as a R/W bit following an address.
2. Set to 1 when the AASX bit is set to 1.
3. When ESTP = 1, STOP is 0, or when STOP = 1, ESTP is 0.
AASX AL
0
0
1↑/0 *
2
0
0
0
0
0↓
0
0
0
0
0↓
1↑/0 *
2
0
0
0
1↑/0 *
2
0
0
0
0
0↓
0
0
0
0
0↓
1↑/0 *
2
0
0
0
1↑/0 *
0/1↑ *
3
3
Section 17 I
AAS
ADZ
ACKB ICDRE ICDRF State
0
1↑
0
0
1↑
0↓
0
0
0↓
0
0
1
0↓
0
0
0↓
0
0
0
1↑
0↓
0↓
0↓
0↓
0
0
0↓
Rev. 3.00 Jan 25, 2006 page 491 of 872
2
C Bus Interface (IIC)
Transmission end (when ACKB
= 1 received)
Transmission end (when
previous state is ICDRE = 0)
Write to ICDR in above state
Transmission end (when
previous state is ICDRE = 1)
Write to ICDR in above state or
after start condition is detected
Data transfer from transmit
buffer to shift register
(automatic) in above state
1↑
Reception end (when previous
state is ICDRF = 0)
0↓
Write to ICDR in above state
1
Reception end (when previous
state is ICDRF = 1)
0↓
Write to ICDR in above state
1↑
Data transfer from shift register
to receive buffer (automatic) in
above state
Stop condition detected
REJ09B0286-0300
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