Renesas H8S/2158 User Manual page 27

13.4 Operation........................................................................................................................... 330
13.4.1 Pulse Output......................................................................................................... 330
13.5 Operation Timing.............................................................................................................. 331
13.5.1 TCNT Count Timing............................................................................................ 331
13.5.2 Timing of CMFA and CMFB Setting at Compare-Match ................................... 332
13.5.3 Timing of Timer Output at Compare-Match........................................................ 332
13.5.4 Timing of Counter Clear at Compare-Match ....................................................... 333
13.5.5 TCNT External Reset Timing .............................................................................. 333
13.5.6 Timing of Overflow Flag (OVF) Setting ............................................................. 334
13.6 TMR_0 and TMR_1 Cascaded Connection ...................................................................... 335
13.6.1 16-Bit Count Mode .............................................................................................. 335
13.6.2 Compare-Match Count Mode .............................................................................. 335
13.7 Input Capture Operation.................................................................................................... 336
13.8 Interrupt Sources ............................................................................................................... 338
13.9 Usage Notes ...................................................................................................................... 339
13.9.1 Conflict between TCNT Write and Clear ............................................................ 339
13.9.2 Conflict between TCNT Write and Increment ..................................................... 340
13.9.3 Conflict between TCOR Write and Compare-Match........................................... 341
13.9.4 Conflict between Compare-Matches A and B...................................................... 342
13.9.5 Switching of Internal Clocks and TCNT Operation............................................. 342
13.9.6 Mode Setting with Cascaded Connection ............................................................ 344
Section 14 Timer Connection
14.1 Features ............................................................................................................................. 345
14.2 Input/Output Pins .............................................................................................................. 347
14.3 Register Descriptions ........................................................................................................ 347
14.3.1 Timer Connection Register I (TCONRI) ............................................................. 348
14.3.2 Timer Connection Register O (TCONRO) .......................................................... 352
14.3.3 Timer Connection Register S (TCONRS)............................................................ 354
14.3.4 Edge Sense Register (SEDGR) ............................................................................ 356
14.4 Operation........................................................................................................................... 358
14.4.1 PWM Decoding (PDC Signal Generation) .......................................................... 358
14.4.2 Clamp Waveform Generation (CL1/CL2/CL3 Signal Generation) ..................... 359
14.4.3 8-Bit Timer Divided Waveform Period Measurement......................................... 361
14.4.4 IHI Signal and 2fH Modification ......................................................................... 363
14.4.5 IVI Signal Fall Modification and IHI Synchronization........................................ 365
14.4.6 Internal Synchronization Signal Generation (IHG/IVG/CL4 Signal Generation) 367
14.4.7 HSYNCO Output ................................................................................................. 370
14.4.8 VSYNCO Output ................................................................................................. 371
14.4.9 CBLANK Output ................................................................................................. 372
........................................................................................... 345
Rev. 3.00 Jan 25, 2006 page xxv of lii