Renesas H8S/2158 User Manual page 411

Bit Bit Name Initial Value
3 VFEDG 0
2 PREDG 0
Undefined *
1 IHI
Undefined *
0 IVI
Notes: 1. Only 0 can be written, to clear the flag.
2. The initial value is undefined since it depends on the pin state.
R/W Description
R/(W) * 1
VFBACKI Edge
Detects a rising edge on the VFBACKI pin.
[Clearing condition]
When 0 is written in VFEDG after reading VFEDG = 1
[Setting condition]
When a rising edge is detected on the VFBACKI pin
R/(W) * 1
Pre-Equalization Flag
Detects the occurrence of an IHI signal 2fH
modification condition. The generation of a
falling/rising edge in the IHI signal during a mask
interval is expressed as the occurrence of a 2fH
modification condition. For details, see section 14.4.4,
IHI Signal and 2fH Modification.
[Clearing condition]
When 0 is written in PREQF after reading PREQF = 1
[Setting condition]
When an IHI signal 2fH modification condition is
detected
2
R IHI Signal Level
Indicates the current level of the IHI signal. Signal
source and phase inversion selection for the IHI
signal depends on the contents of TCONRI. Read this
bit to determine whether the input signal is positive or
negative, then maintain the IHI signal at positive
phase by modifying TCONRI.
0: The IHI signal is low
1: The IHI signal is high
2
R IVI Signal Level
Indicates the current level of the IVI signal. Signal
source and phase inversion selection for the IVI
signal depends on the contents of TCONRI. Read this
bit to determine whether the input signal is positive or
negative, then maintain the IVI signal at positive
phase by modifying TCONRI.
0: The IVI signal is low
1: The IVI signal is high
Section 14 Timer Connection
Rev. 3.00 Jan 25, 2006 page 357 of 872
REJ09B0286-0300