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17.7
Usage Notes
1. In master mode, if an instruction to generate a start condition is immediately followed by an
instruction to generate a stop condition, neither condition will be output correctly. To output
consecutive start and stop conditions, after issuing the instruction that generates the start
condition, read the relevant ports, check that SCL and SDA are both low, then issue the
instruction that generates the stop condition. Note that SCL may not yet have gone low when
BBSY is cleared to 0.
2. Either of the following two conditions will start the next transfer. Pay attention to these
conditions when accessing to ICDR.
Write to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from transmit
buffer to shift register)
Read from ICDR when ICE = 1 and TRS = 0 (including automatic transfer from shift
register to receive buffer)
3. Table 17.11 shows the timing of SCL and SDA outputs in synchronization with the internal
clock. Timings on the bus are determined by the rise and fall times of signals affected by the
bus load capacitance, series resistance, and parallel resistance.
2
Table 17.11 I
C Bus Timing (SCL and SDA Outputs)
Item
SCL output cycle time
SCL output high pulse width
SCL output low pulse width
SDA output bus free time
Start condition output hold time
Retransmission start condition output
setup time
Stop condition output setup time
Data output setup time (master)
Data output setup time (slave)
Data output hold time
Note:
* 6 t
when IICX is 0, 12 t
cyc
4. SCL and SDA inputs are sampled in synchronization with the internal clock. The AC timing
therefore depends on the system clock cycle t
interface AC timing specifications will not be met with a system clock frequency of less than
5 MHz.
Symbol
Output Timing
t
28 t
SCLO
cyc
t
0.5 t
SCLHO
SCLO
t
0.5 t
SCLLO
SCLO
t
0.5 t
BUFO
SCLO
t
0.5 t
STAHO
SCLO
t
1 t
STASO
SCLO
t
0.5 t
STOSO
SCLO
t
1 t
SDASO
SCLLO
1 t
SCLL
t
3 t
SDAHO
cyc
when 1.
cyc
, as shown in table 29.10. Note that the I
cyc
Rev. 3.00 Jan 25, 2006 page 541 of 872
2
Section 17 I
C Bus Interface (IIC)
Unit
to 256 t
ns
cyc
ns
ns
– 1 t
ns
cyc
– 1 t
ns
cyc
ns
+ 2 t
ns
cyc
– 3 t
ns
cyc
* )
– (6 t
or 12 t
cyc
cyc
ns
REJ09B0286-0300
Notes
2
C bus
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