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Section 19 Multimedia Card Interface (MCIF)
19.3.7
Response Registers 0 to 16, and D (RSPR0 to RSPR16, and RSPRD)
The RSPR registers are eighteen 8-bit registers. RSPR0 to RSPR16 are command response
registers. RSPRD is a data response register that is used in only SPI mode.
The number of command response bytes differs according to the command. The number of
command response bytes can be specified by RSPTYR in the MCIF. The command response is
shifted-in from bit 0 in RSPR16, and shifted to the number of command response bytes × 8 bits.
Table 19.4 summarizes the correspondence between the number of command response bytes and
valid RSPR register.
The data response is shifted-in from bit 0 in RSPRD, and shifted 8 bits only when a command
includes write data in SPI mode. For other commands, the data response is not shifted. RSPRD is
cleared to H'00 by writing an arbitrary value *
The initial value of the RSPR registers is H'00. RSPR0 to RSPR16 are simple shift registers. A
command response that has been shifted in is not automatically cleared, and is continuously
shifted until it is shifted out from bit 7 in RSPR0. To clear unnecessary bytes to H'00, write
arbitrary values to each RSPR *
Notes: 1. Bits 7 to 5 in RSPRD are fixed at 0.
2. Reading the data response from RSPR should be executed after one transfer clock
cycle following the DRPI interrupt occurrence. Clearing of RSPR is completed after
two transfer clock cycles following the write of arbitrary values.
Rev. 3.00 Jan 25, 2006 page 638 of 872
REJ09B0286-0300
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