Figure 17.15 Iric Flag Timing And Scl Control (3) - Renesas H8S/2158 User Manual

16-bit single-chip microcomputer h8s family/h8s/2100 series
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When FS = 1 while FSX = 1 (synchronous serial format)
SCL
7
SDA
7
IRIC
User processing
(a) Data transfer ends with ICDRE = 0 for transmission or ICDRF = 0 for reception
SCL
7
SDA
7
IRIC
User processing
(b) Data transfer ends with ICDRE = 1 for transmission or ICDRF = 1 for reception

Figure 17.15 IRIC Flag Timing and SCL Control (3)

8
1
2
8
1
2
Clear IRIC
8
8
Clear IRIC
Write to ICDR (transmit)
or read from ICDR (receive)
Rev. 3.00 Jan 25, 2006 page 529 of 872
2
Section 17 I
C Bus Interface (IIC)
3
4
3
4
1
1
Clear IRIC
REJ09B0286-0300

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