Rfu Bus Cycle Insertion; Rfu Response Time; Table 8.5 Bus Cycle Insertion - Renesas H8S/2158 User Manual

8.7.2

RFU Bus Cycle Insertion

The RFU bus cycle can be inserted at a break in the bus cycle under almost all conditions.
Table 8.5 summarizes a comparison of enabling/disabling bus cycle insertion for the DTC and
RFU. The RFU bus cycle can be inserted with the same condition as the DTC when the BUSDIVE
bit in BCR2 is cleared to 0.
Table 8.5 Bus Cycle Insertion
Bus Cycle Condition
CPU internal operation cycle
The end of CPU bus cycle
The end of upper-byte CPU bus cycle for divided word access
The end of upper-word CPU bus cycle for divided long word access
The end of each CPU bus cycle for EEPMOV instruction
The end of each CPU bus cycle for STM/LDM instruction
The end of each CPU bus cycle for bit manipulation instruction
The end of CPU bus cycle for CCR manipulation instruction
The end of each CPU bus cycle for stacking/unstacking processing
The end of each CPU bus cycle for vector address read
The end of each DTC bus cycle for vector address read
The end of accessing DTC control register (32 bits × 3)
The end of the first and second long word bus cycles for accessing
DTC control register (32 bits × 3)
The end of DTC bus cycle
The end of upper-byte DTC bus cycle for divided word access
8.7.3

RFU Response Time

Figure 8.3 shows an example of the RFU response time. The RFU response time consists of the
following:
• Cycle to synchronize peripheral module signals with the system clock: 1 and 2 states
• Cycle to output a request from the peripheral modules: 1 to 5 states
• Cycle to wait for the end of the current bus cycle: 0 to 2 states (except for wait states for
external extension)
Section 8 RAM-FIFO Unit (RFU)
RFU
Enabled
Enabled
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Rev. 3.00 Jan 25, 2006 page 189 of 872
DTC
Enabled
Enabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
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—
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REJ09B0286-0300