Input/Output Pins; Register Descriptions; Figure 17.2 I 2 C Bus Interface Connections (Example: This Lsi As Master); Table 17.1 Pin Configuration - Renesas H8S/2158 User Manual

2
Section 17 I C Bus Interface (IIC)
V
CC
V
CC
SCL
in
SCL
out
SDA
in
SDA
out
(Master)
This LSI
Figure 17.2 I
17.2

Input/Output Pins

Table 17.1 summarizes the input/output pins used by the I

Table 17.1 Pin Configuration

Channel Symbol
0 SCL0
SDA0
1 SCL1
SDA1
17.3

Register Descriptions

2
The I C bus interface has the following registers. Registers ICDR and SARX and registers ICMR
and SAR are allocated to the same addresses. Accessible registers differ depending on the ICE bit
in ICCR. When the ICE bit is cleared to 0, SAR and SARX can be accessed, and when the ICE bit
is set to 1, ICMR and ICDR can be accessed. For details on the serial timer control register, see
section 3.2.3, Serial Timer Control Register (STCR).
Rev. 3.00 Jan 25, 2006 page 476 of 872
REJ09B0286-0300
V
DD
SCL
SDA
SCL
in
SCL
out
SDA
in
SDA
out
(Slave 1)
2
C Bus Interface Connections (Example: This LSI as Master)
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
SCL
in
SCL
out
SDA
in
SDA
out
(Slave 2)
2
C bus interface.
Function
Clock input/output pin of channel 0
Data input/output pin of channel 0
Clock input/output pin of channel 1
Data input/output pin of channel 1
SCL
SDA