Figure 16.41 Pin States During Transmission In Clocked Synchronous Mode (Internal Clock); Figure 16.42 Sample Flowchart For Mode Transition During Reception - Renesas H8S/2158 User Manual

TE bit
SCK
output pin
TxD
Port
input/output
output pin
Port
Note: * Initialized in software standby mode
Figure 16.41 Pin States during Transmission in Clocked Synchronous Mode
Reception
Read RDRF flag in SSR
RDRF = 1
Yes
Read receive data in RDR
Make transition to software standby mode etc.
Cancel software standby mode etc.
Change operating mode?
Yes
Initialization
Start reception

Figure 16.42 Sample Flowchart for Mode Transition during Reception

Section 16 Serial Communication Interface (SCI, IrDA, and CRC)
Transmission start
Marking output
SCI TxD output
(Internal Clock)
No
RE = 0
No
Transmission end
Last TxD bit retained
[1] [1] Data being received will be invalid.
[2] Module stop, watch, sub-active, and sub-
sleep modes are included.
[2]
RE = 1
Rev. 3.00 Jan 25, 2006 page 465 of 872
Transition to
Software standby
software standby
mode cancelled
mode
Port
input/output
High output *
Port input/output
Port
REJ09B0286-0300
SCI
TxD output