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Section 15 Watchdog Timer (WDT)
If the RST/NMI bit of TCSR is set to 1, when the TCNT overflows, an internal reset signal for this
LSI is issued for 518 system clocks, and the low level signal is simultaneously output from the
RESO pin for 132 states, as shown in figure 15.2. If the RST/NMI bit is cleared to 0, when the
TCNT overflows, an NMI interrupt request is generated. Here, the output from the RESO pin
remains high.
An internal reset request from the watchdog timer and a reset input from the RES pin are
processed in the same vector. Reset source can be identified by the XRST bit status in SYSCR.
If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a
WDT overflow, the RES pin reset has priority and the XRST bit in SYSCR is set to 1.
An NMI interrupt request from the watchdog timer and an interrupt request from the NMI pin are
processed in the same vector. Do not handle an NMI interrupt request from the watchdog timer
and an interrupt request from the NMI pin at the same time.
H'FF
H'00
Internal reset signal
Legend:
WT/IT:
Timer mode select bit
TME:
Timer enable bit
OVF:
Overflow flag
Note: * After the OVF bit becomes 1, it is cleared to 0 by an internal reset.
The XRST bit is also cleared to 0.
Figure 15.2 Watchdog Timer Mode (RST/NMI
Rev. 3.00 Jan 25, 2006 page 380 of 872
REJ09B0286-0300
TCNT value
WT/IT = 1
Write H'00 to
TME = 1
TCNT
Overflow
OVF = 1 *
WT/IT = 1
TME = 1
518 System clocks
NMI = 1) Operation
NMI
NMI
Time
Write H'00 to
TCNT
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