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16.3.9 Bit Rate
Register (BRR)
Table 16.2
Relationship between
N Setting in BRR and
Bit Rate B
16.3.10 Serial
Interface Control
Register (SCICR)
16.7.8 Clock Output
Control
16.8 IrDA Operation
Figure 16.36 IrDA
Block Diagram
Page
Revision (See Manual for Details)
405
Table 16.2 amended
Mode
Smart card
interface mode
412
Table amended
Bit
Bit Name
3, 2
—
1, 0
—
455
Description amended
At Transition from Smart Card Interface Mode to Software
Standby Mode:
1. Set the port data register (DR) ...
At Transition from Software Standby Mode to Smart Card
Interface Mode:
1. Cancel software standby mode. ...
456
Figure 16.36 amended
TxD1/IrTxD
RxD1/IrRxD
Description amended
Transmission: ... The high-level pulse can be selected using
the IrCKS2 to IrCKS0 bits in SCICR.
457
Description amended
Reception: ... IR frames are converted to UART frames using
the IrDA interface before inputting to SCI_1. Data of level 0 is ...
Bit Rate
Error
φ × 10
6
B =
Error (%) =
S × 2
× (N + 1)
2n + 1
Initial Value
R/W
Description
All 0
R/W
Reserved
The initial value should not be changed.
All 0
R
Reserved
These bits are always read as 0 and cannot be
modified.
IrDA
Pulse encoder
Pulse decoder
SCICR
Rev. 3.00 Jan 25, 2006 page xi of lii
φ × 10
6
– 1 × 100
B × S × 2
× (N + 1)
2n + 1
SCI_1
TxD1
RxD1
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