Renesas H8S/2158 User Manual page 42

Figure 16.18 Sample SCI Initialization Flowchart..................................................................... 438
Figure 16.19 Sample SCI Transmission Operation in Clocked Synchronous Mode.................. 439
Figure 16.20 Sample Serial Transmission Flowchart................................................................. 440
Figure 16.21 Example of SCI Receive Operation in Clocked Synchronous Mode.................... 441
Figure 16.22 Sample Serial Reception Flowchart...................................................................... 442
Figure 16.23 Sample Flowchart of Simultaneous Serial Transmission and Reception.............. 444
Figure 16.24 Pin Connection for Smart Card Interface.............................................................. 445
Figure 16.25 Data Formats in Normal Smart Card Interface Mode........................................... 446
Figure 16.26 Direct Convention (SDIR = SINV = O/E = 0)...................................................... 446
Figure 16.27 Inverse Convention (SDIR = SINV = O/E = 1) .................................................... 447
Figure 16.28 Receive Data Sampling Timing in Smart Card Interface Mode
(When Clock Frequency Is 372 Times the Bit Rate) ............................................ 448
Figure 16.29 Data Re-transfer Operation in SCI Transmission Mode ....................................... 451
Figure 16.30 TEND Flag Set Timings during Transmission ..................................................... 451
Figure 16.31 Sample Transmission Flowchart........................................................................... 452
Figure 16.32 Data Re-transfer Operation in SCI Reception Mode ............................................ 453
Figure 16.33 Sample Reception Flowchart ................................................................................ 454
Figure 16.34 Clock Output Fixing Timing................................................................................. 455
Figure 16.35 Clock Stop and Restart Procedure ........................................................................ 456
Figure 16.36 IrDA Block Diagram ............................................................................................ 456
Figure 16.37 IrDA Transmission and Reception........................................................................ 457
Figure 16.38 Sample Transmission using DTC in Clocked Synchronous Mode ....................... 463
Figure 16.39 Sample Flowchart for Mode Transition during Transmission .............................. 464
Figure 16.40 Pin States during Transmission in Asynchronous Mode (Internal Clock) ............ 464
Figure 16.41 Pin States during Transmission in Clocked Synchronous Mode
(Internal Clock)..................................................................................................... 465
Figure 16.42 Sample Flowchart for Mode Transition during Reception.................................... 465
Figure 16.43 Switching from SCK Pins to Port Pins ................................................................. 466
Figure 16.44 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins ......... 466
Figure 16.45 Block Diagram of CRC Operation Circuit............................................................ 467
Figure 16.46 LSB-First Data Transmission ............................................................................... 469
Figure 16.47 MSB-First Data Transmission .............................................................................. 469
Figure 16.48 LSB-First Data Reception..................................................................................... 470
Figure 16.49 MSB-First Data Reception.................................................................................... 471
Figure 16.50 LSB-First and MSB-First Transmit Data.............................................................. 472
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Section 17 I C Bus Interface (IIC)
Figure 17.1 Block Diagram of I
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Figure 17.2 I C Bus Interface Connections (Example: This LSI as Master)............................ 476
Figure 17.3 State Transitions of TDRE, SDRF, and RDRF Bits ............................................. 507
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Figure 17.4 I C Bus Data Formats (I
Rev. 3.00 Jan 25, 2006 page xl of lii
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C Bus Interface ..................................................................... 475
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C Bus Formats) ............................................................. 516