Location Of Register Information And Dtc Vector Table; Figure 7.3 Dtc Register Information Location In Address Space - Renesas H8S/2158 User Manual

7.4

Location of Register Information and DTC Vector Table

Locate the register information in the on-chip RAM (addresses: H'(FF)EC00 to H'(FF)EFFF).
Register information should be located at an address that is a multiple of four within the range.
The method for locating the register information in address space is shown in figure 7.3. Locate
MRA, SAR, MRB, DAR, CRA, and CRB, in that order, from the start address of the register
information. In the case of chain transfer, register information should be located in consecutive
areas as shown in figure 7.3, and the register information start address should be located at the
vector address corresponding to the interrupt source in the DTC vector table. The DTC reads the
start address of the register information from the vector table set for each activation source, and
then reads the register information from that start address.
When the DTC is activated by software, the vector address is obtained from: H'0400 +
(DTVECR[6:0] × 2). For example, if DTVECR is H'10, the vector address is H'0420.
The configuration of the vector address is the same in both normal and advanced modes; a 2-byte
unit is used in both cases. Specify the lower two bits of the register information start address.
Register
information
start address
Chain
transfer

Figure 7.3 DTC Register Information Location in Address Space

Lower address
0 1
MRA
MRB
CRA
MRA
MRB
CRA
4 bytes
Section 7 Data Transfer Controller (DTC)
2 3
SAR
DAR
CRB
SAR
DAR
CRB
Rev. 3.00 Jan 25, 2006 page 153 of 872
Register information
Register information
for 2nd transfer in
chain transfer
REJ09B0286-0300