Figure 14.1 Block Diagram Of Timer Connection - Renesas H8S/2158 User Manual

Section 14 Timer Connection
Edge
detection
Phase
VSYNCI/
FTIA inversion
Edge
detection
Phase
VFBACKI/
inversion
FTIB
FTIC
Phase
HSYNCI/
inversion
TMI1
Edge
detection
Phase
CSYNCI/
inversion
FTID
Edge
detection
Phase
HFBACKI/
inversion
FTCI
Edge
detection
TMIX
Rev. 3.00 Jan 25, 2006 page 346 of 872
REJ09B0286-0300
Read
flag
IVI signal
IVI
signal
SET
selection
sync
RES
FTIA
FRT
FTIB
input
selection
FTIC
FTID
TMR_Y
signal
selection
TMR_1
signal
selection
IHI signal
IVI
TMR_X
signal
TMCI/
input
selection
selection TMRI
CM1C
Clamp waveform generation
Read
flag

Figure 14.1 Block Diagram of Timer Connection

VSYNC
modify
16-bit FRT
FTOA
CMA(R) SET
OCRA +VR, +VF
ICRD +1M, +2M
CMA(F) RES
compare match
FTOB
CM1M CM2M
SET RES
2f H mask generation
2f H mask flag
Blank waveform generation
TMRI/TMCI
IHG signal
8-bit TMR_Y
TMO
CMB
TMCI
8-bit
TMO
TMR_1
TMRI
PDC signal
PWM decoding
CMB
8-bit TMR_X
ICR
TMO
ICR +1C
compare match
CMA
CL1 signal
CL2 signal
CL3 signal
IVO
Phase
signal
inversion
selection
FRT
output
selection
A
IVG signal IVO signal
FRT
output
selection
B
Phase
CBLANK
inversion
TMOY
Phase
TMO1
inversion
IHO
output
signal
selection
selection
B
CL4 generation
CL4 signal
CLO
signal
Phase
selection
inversion
VSYNCO/
FTOA
HSYNCO/
TMO1
TMOX
CLAMPO/
FTIC