Iic Operation Reservation Adapter Status Register C (Icsrc) - Renesas H8S/2158 User Manual

16-bit single-chip microcomputer h8s family/h8s/2100 series
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2
Section 17 I
C Bus Interface (IIC)

17.3.10 IIC Operation Reservation Adapter Status Register C (ICSRC)

ICSRC monitors the transmission/reception status of the IIC operation reservation adapter. See
figure 17.3 for details on the TDRE, SDRF, and RDRF bits.
Bit
Bit Name
Initial Value
7
MTREQ
0
6
MRREQ
0
Rev. 3.00 Jan 25, 2006 page 502 of 872
REJ09B0286-0300
R/W
Description
R/(W) *
1
Master Mode Transmit Data Write Request Interrupt Flag
0: No transmit data write request is generated in master
mode
1: A transmit data write request is generated and an
interrupt is requested in master mode
[Clearing conditions]
When ICDRX is written to
When ICCMD is written to
When 0 is written to MTREQ after reading MTREQ =
1
[Setting condition]
When data transmission is completed in master mode
R/(W) *
1
Master Mode Receive Data Read Request Interrupt Flag
0: No receive data read request is generated in master
mode
1: A receive data read request is generated and an
interrupt is requested in master mode
[Clearing conditions]
When ICDRX is written to
When ICCMD is written to
When 0 is written to MRREQ after reading MRREQ =
1
[Setting condition]
When data reception is completed in master mode

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