Interrupt Status Registers 0, 1 (Intstr0, Intstr1) - Renesas H8S/2158 User Manual

19.3.14 Interrupt Status Registers 0, 1 (INTSTR0, INTSTR1)

The INTSTR registers enable or disable the MCIFI0 to MCIFI2 interrupt requests of MCIF.
INTSTR0
Bit Bit Name
7 FEI
6 FFI
5 DRPI
Initial Value R/W
R/(W) *
0
R/(W) *
0
R/(W) *
0
Section 19 Multimedia Card Interface (MCIF)
Description
FIFO Empty Interrupt Flag
0: No interrupts
1: MCIFI0 interrupt requested.
[Setting condition]
•
When transmit data FIFO becomes empty
while FEIE = 1 in INTCR0 (when the
FIFO_EMPTY bit in CSTR is set)
[Clearing condition]
•
Write 0 after reading FEI = 1.
FIFO Full Interrupt Flag
0: No interrupts
1: MCIFI0 interrupt requested.
[Setting condition]
•
When receive data FIFO becomes full while
FFIE = 1 in INTCR0 (when the FIFO_FULL
bit in CSTR is set)
[Clearing condition]
•
Write 0 after reading FFI = 1.
Data Response Interrupt Flag
0: No interrupts
1: MCIFI1 interrupt requested.
[Setting condition]
•
If DRPIE = 1 in INTCR0, when CRC status
(in MMC mode) or data response (in SPI
mode) is received from the MMC after
single-block transmission.
[Clearing condition]
•
Write 0 after reading DRPI = 1.
Rev. 3.00 Jan 25, 2006 page 649 of 872
REJ09B0286-0300