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25.2
Input/Output Pins
Table 25.1 shows the H-UDI pin configuration.
Table 25.1 Pin Configuration
Pin Name
Abbreviation
Test clock
ETCK
Test mode select
ETMS
Test data input
ETDI
Test data output
ETDO
ETRST
Test reset
Section 25 User Debug Interface (H-UDI)
I/O
Function
Input
Test clock input
Provides an independent clock supply to the H-
UDI. As the clock input to the ETCK pin is
supplied directly to the H-UDI, a clock waveform
with a duty cycle close to 50% should be input.
For details, see section 29, Electrical
Characteristics. If there is no input, the ETCK pin
is fixed to 1 by an internal pull-up.
Input
Test mode select input
Sampled on the rise of the ETCK pin. The ETMS
pin controls the internal state of the TAP
controller. If there is no input, the ETMS pin is
fixed to 1 by an internal pull-up.
Input
Serial data input
Performs serial input of instructions and data for
H-UDI registers. ETDI is sampled on the rise of
the ETCK pin. If there is no input, the ETDI pin is
fixed to 1 by an internal pull-up.
Output
Serial data output
Performs serial output of instructions and data
from H-UDI registers. Transfer is performed in
synchronization with the ETCK pin. If there is no
output, the ETDO pin goes to the high-
impedance state.
Input
Test reset input signal
Initializes the H-UDI asynchronously. If there is
no input, the ETRST pin is fixed to 1 by an
internal pull-up.
Rev. 3.00 Jan 25, 2006 page 743 of 872
REJ09B0286-0300
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