Timing Of On-Chip Peripheral Modules; Table 24.8 Timing Of On-Chip Peripheral Modules - Renesas H8S/2437 Hardware Manual

24.3.4

Timing of On-Chip Peripheral Modules

Tables 24.8 to 24.10 show the on-chip peripheral module timing.

Table 24.8 Timing of On-Chip Peripheral Modules

Condition: V = 3.0 V to 3.6 V, V
CC
Item
I/O ports Output data delay time
Input data setup time
Input data hold time
FRT Timer output delay time
Timer input setup time
Timer clock input setup time
Timer clock pulse
width
TPU Timer output delay time
Timer input setup time
Timer clock input setup time
Timer clock pulse
width
TMR Timer output delay time
Timer reset input setup time
Timer clock input setup time
Timer clock pulse
width
PWM, Pulse output delay time
PWMX
SCI Input clock cycle
Input clock pulse width
Input clock rise time
Input clock fall time
Transmit data delay time
(synchronous)
Receive data setup time
(synchronous)
Receive data hold time (synchronous) t
A/D Trigger input setup time
converter
= 0 V, φ = 5 MHz to 20 MHz
SS
Symbol Min.
t
PWD
t
PRS
t
PRH
t
FTOD
t
FTIS
t
FTCS
Single edge t
FTCWH
Both edges t
FTCWL
t
TOCD
t
TICS
t
TCKS
Single edge t
TCKWH
Both edges t
TCKWL
t
TMOD
t
TMRS
t
TMCS
Single edge t
TMCWH
Both edges t
TMCWL
t
PWOD
Asynchronous t
Scyc
Synchronous
t
SCKW
t
SCKr
t
SCKf
t
TXD
t
RXS
RXH
t
TRGS
Max. Unit

40 ns

20

20

40

20

20

1.5 t
cyc

2.5

40 ns

25

25

1.5 t
cyc

2.5

40 ns

25

25

1.5 t
cyc

2.5

40 ns

4 t
cyc

6
0.4 0.6 t
Scyc

1.5 t
cyc

1.5

40 ns

40

40

30
Rev. 1.00, 09/03, page 685 of 704
Test Conditions
Figure 24.14
Figure 24.15
Figure 24.16
Figure 24.17
Figure 24.18
Figure 24.19
Figure 24.21
Figure 24.20
Figure 24.22
Figure 24.23
Figure 24.24
Figure 24.25