Renesas H8S/2158 User Manual page 648

Section 18 Universal Serial Bus Interface (USB)
USBCR1
Bit Bit Name Initial Value R/W
7 to — All 0
2
1 VBUSS 0
0 CK48- 0
READY
Rev. 3.00 Jan 25, 2006 page 594 of 872
REJ09B0286-0300
Description
R Reserved
These bits are always read as 0 and cannot be modified.
R/W VBUS Status
Prevents bus driver/receiver feedthrough current from
generating by controlling the VBUS line (USB cable)
connection state. The VBUS status monitor circuit must
be designed by using the external interrupt and general
ports. In addition, external pull-up resistors must be
turned ON or OFF by using the general ports.
0: Prevents feedthrough current from generating by
disconnecting VBUS.
The USDP and USDM pins are placed in high-
impedance state.
1: VBUS connection.
The USDP and USDM pins are pulled up and pulled
down, respectively.
R/W CK48READY
Controls the bus clock (48 MHz) supply to the USB
function core. To stop or start up the PLL operation
correctly in suspend or resume state, the bus clock
supply must be stopped before stopping the PLL circuit,
and the bus clock supply must be restarted after the PLL
operation is stabilized.
0: Disables the bus clock supply to the USB function core
1: Enables the bus clock supply to the USB function core