Renesas H8S/2158 User Manual page 40

Figure 12.9 Buffered Input Capture Timing ............................................................................ 303
Figure 12.10 Buffered Input Capture Timing (BUFEA = 1)...................................................... 304
Figure 12.11 Timing of Input Capture Flag (ICFA, ICFB, ICFC, or ICFD) Setting ................. 304
Figure 12.12 Timing of Output Compare Flag (OCFA or OCFB) Setting ................................ 305
Figure 12.13 Timing of Overflow Flag (OVF) Setting .............................................................. 306
Figure 12.14 OCRA Automatic Addition Timing...................................................................... 306
Figure 12.15 Timing of Input Capture Mask Signal Setting ...................................................... 307
Figure 12.16 Timing of Input Capture Mask Signal Clearing.................................................... 307
Figure 12.17 FRC Write-Clear Conflict..................................................................................... 309
Figure 12.18 FRC Write-Increment Conflict ............................................................................. 310
Figure 12.19 Conflict between OCR Write and Compare-Match
(When Automatic Addition Function Is Not Used) .............................................. 311
Figure 12.20 Conflict between OCR Write and Compare-Match
(When Automatic Addition Function Is Used) ..................................................... 312
Section 13 8-Bit Timer (TMR)
Figure 13.1 Block Diagram of 8-Bit Timer (TMR_0 and TMR_1) ......................................... 316
Figure 13.2 Block Diagram of 8-Bit Timer (TMR_Y and TMR_X) ....................................... 317
Figure 13.3 Pulse Output Example .......................................................................................... 330
Figure 13.4 Count Timing for Internal Clock Input ................................................................. 331
Figure 13.5 Count Timing for External Clock Input................................................................ 331
Figure 13.6 Timing of CMF Setting at Compare-Match.......................................................... 332
Figure 13.7 Timing of Toggled Timer Output by Compare-Match A Signal .......................... 332
Figure 13.8 Timing of Counter Clear by Compare-Match....................................................... 333
Figure 13.9 Timing of Counter Clear by External Reset Input ................................................ 333
Figure 13.10 Timing of OVF Flag Setting ................................................................................. 334
Figure 13.11 Timing of Input Capture Operation ...................................................................... 336
Figure 13.12 Timing of Input Capture Signal
(Input Capture Signal Is Input during TICRR and TICRF Read) ......................... 337
Figure 13.13 Input Capture Signal Selection ............................................................................. 337
Figure 13.14 Conflict between TCNT Write and Clear ............................................................. 340
Figure 13.15 Conflict between TCNT Write and Increment...................................................... 340
Figure 13.16 Conflict between TCOR Write and Compare-Match............................................ 341
Section 14 Timer Connection
Figure 14.1 Block Diagram of Timer Connection.................................................................... 346
Figure 14.2 Timing Chart for PWM Decoding ........................................................................ 359
Figure 14.3 Timing Chart for Clamp Waveform Generation (CL1 and CL2 Signals)............. 360
Figure 14.4 Timing Chart for Clamp Waveform Generation (CL3 Signal) ............................. 360
Figure 14.5 Timing Chart for Measurement of IVI Signal and IHI Signal Divided
Waveform Periods ................................................................................................ 363
Rev. 3.00 Jan 25, 2006 page xxxviii of lii