Port 9 Data Register (P9Dr); Pin Functions - Renesas H8S/2158 User Manual

9.9.2

Port 9 Data Register (P9DR)

P9DR stores output data for the port 9 pins.
Bit Bit Name
7 P97DR
6 P96DR
5 P95DR
4 P94DR
3 P93DR
2 P92DR
1 P91DR
0 P90DR
Note: * The initial value of bit 6 is determined according to the P96 pin state.
9.9.3

Pin Functions

The relationship between the operating mode, register setting values, and pin functions are as
follows. In the tables, the symbol "—" stands for Don't care.
• P97/WAIT/CPWAIT/CS256
The pin function is switched as shown below according to the combination of the operating
mode, the CS256E bit in SYSCR, the WMS1 bit in WSCR, the WMS21 bit in WSCR2, and
the P97DDR bit.
Operating
Mode
WMS1,
WMS21
CS256E
P97DDR
Pin function P97 input
pin
Initial Value R/W
0 R/W
Undefined *
R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Extended Mode
All bits are set as 0
0
0 1
P97 output
pin output pin
Description
P9DR stores output data for the port 9 pins that
are used as the general output port except for bit
6.
If a port 9 read is performed while the P9DDR bits
are set to 1, the P9DR values are read. If a port 9
read is performed while the P9DDR bits are
cleared to 0, the pin states are read.
One bit is set as 1
1 —
— —
CS256 WAIT (WMS1 = 1)
and CPWAIT
(WMS21 = 1) input
pins
Rev. 3.00 Jan 25, 2006 page 251 of 872
Section 9 I/O Ports
Single-Chip Mode
—
—
0 1
P97 P97
input pin output pin
REJ09B0286-0300