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Section 7 Data Transfer Controller (DTC)
7.2.7
DTC Enable Registers (DTCER)
DTCER specifies DTC activation interrupt sources. DTCER is comprised of five registers:
DTCERA to DTCERE. The correspondence between interrupt sources and DTCE bits is shown in
tables 7.1 to 7.3. For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR.
Multiple DTC activation sources can be set at one time (only at the initial setting) by masking all
interrupts and writing data after executing a dummy read on the relevant register.
Bit
Bit Name
Initial Value
7
DTCE7
0
6
DTCE6
0
5
DTCE5
0
4
DTCE4
0
3
DTCE3
0
2
DTCE2
0
1
DTCE1
0
0
DTCE0
0
Table 7.1
Correspondence between Interrupt Sources and DTCER
Bit
Bit Name
DTCERA
7
DTCEn7
(16)IRQ0
6
DTCEn6
(17)IRQ1
5
DTCEn5
(18)IRQ2
4
DTCEn4
(19)IRQ3
3
DTCEn3
(28)ADI
2
DTCEn2
(48)ICIA
1
DTCEn1
(49)ICIB
0
DTCEn0
(52)OCIA
Notes: n:
A to E
( ): Vector number
—: Reserved. The write value should always be 0.
Rev. 3.00 Jan 25, 2006 page 150 of 872
REJ09B0286-0300
R/W
Description
R/W
DTC Activation Enable
R/W
Setting this bit to 1 specifies a relevant interrupt source
R/W
as a DTC activation source.
R/W
[Clearing conditions]
R/W
R/W
•
When data transfer has ended with the DISEL bit in
R/W
MRB set to 1
R/W
•
When the specified number of transfers have ended
These bits are not cleared when the DISEL bit is 0 and
the specified number of transfers have not been
completed
DTCERB
DTCERC
(53)OCIB
(69)CMIB1
(93)IICM0
(72)CMIAY
(94)IICR0
(73)CMIBY
(95)IICT0
—
—
(44)CMIAX
(64)CMIA0
(81)RXI0
(65)CMIB0
(82)TXI0
(68)CMIA1
(85)RXI1
Register
DTCERD
(86)TXI1
(89)RXI2
(90)TXI2
(97)IICM1
(98)IICR1
(99)IICT1
(112)MMCIA
(45)CMIBX
DTCERE
(108)USBI0
(109)USBI1
(110)USBI2
(111)USBI3
—
—
—
—
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