Bus Arbitration; Bus Master Priority; Table 6.11 Pin States In Idle Cycle - Renesas H8S/2158 User Manual

Section 6 Bus Controller
Table 6.11 shows the pin states in an idle cycle.

Table 6.11 Pin States in Idle Cycle

Pins
A17 to A0
D15 to D0
AS, IOS, CS256, CPCS1, CPCS2
RD, CPOE
HWR, LWR, CPWE
6.9

Bus Arbitration

The BSC has a bus arbiter that arbitrates bus master operations. There are three bus masters—the
CPU, DTC, and RFU—that perform read/write operations when they have possession of the bus.
6.9.1

Bus Master Priority

Each bus master requests the bus by means of a bus request signal. The bus arbiter detects the bus
masters' bus request signals, and if a bus request occurs, it sends a bus request acknowledge signal
to the bus master making the request at the designated timing. If there are bus requests from more
than one bus master, the bus request acknowledge signal is sent to the one with the highest
priority. When a bus master receives the bus request acknowledge signal, it takes possession of the
bus until that signal is canceled. The order of priority of the bus masters is as follows:
(High) RFU > DTC > CPU (Low)
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REJ09B0286-0300
Pin State
Contents of immediately following bus cycle
High impedance
High
High
High