Bus Control Register 2 (Bcr2) - Renesas H8S/2158 User Manual

Section 6 Bus Controller
6.3.2

Bus Control Register 2 (BCR2)

BCR2 is used to specify the access mode for the CP expansion area (basic mode) and CF
expansion area (memory card mode).
Bit Bit Name Initial Value
7 OWEAC 0
6 OWENC 0
5 ABWCP 1
Rev. 3.00 Jan 25, 2006 page 108 of 872
REJ09B0286-0300
R/W Description
R/W OE/WE Assert Control
Specifies the number of cycles from address output to
the CPOE and CPWE signal assertion when the CF
expansion area is specified as the CP expansion area.
0: 0.5 cycles
1: 1.5 cycles
If the ASTCP bit is cleared to 0, this bit must not be set
to 1.
R/W OE/WE Negate Control
Specifies the number of delay cycles from CPOE and
CPWE signal negation to address hold when the CF
expansion area is specified as the CP expansion area.
0: 0.5 cycles
1: 1.5 cycles
If the ASTCP bit is cleared to 0, this bit must not be set
to 1.
R/W CP Expansion Area Bus Width Control
Selects the bus width for access to the CP expansion
area when the CPCSE bit in BCR2 is set to 1 while the
CFE bit in BCR is cleared to 0. When the CPCSE bit in
BCR2 is set to 1 while the CFE bit in BCR is set to 1,
the bus width for access to the CF expansion area is
fixed at 16 bits.
0: 16-bit bus
1: 8-bit bus