Renesas H8S/2158 User Manual page 34

24.8.1 Program/Program-Verify ..................................................................................... 733
24.8.2 Erase/Erase-Verify............................................................................................... 735
24.9 Program/Erase Protection.................................................................................................. 737
24.9.1 Hardware Protection ............................................................................................ 737
24.9.2 Software Protection.............................................................................................. 737
24.9.3 Error Protection.................................................................................................... 737
24.10 Interrupts during Flash Memory Programming/Erasing ................................................... 738
24.11 Programmer Mode ............................................................................................................ 738
24.12 Usage Notes ...................................................................................................................... 739
Section 25 User Debug Interface (H-UDI)
25.1 Features ............................................................................................................................. 741
25.2 Input/Output Pins .............................................................................................................. 743
25.3 Register Descriptions ........................................................................................................ 744
25.3.1 Instruction Register (SDIR) ................................................................................. 744
25.3.2 Bypass Register (SDBPR) ................................................................................... 746
25.3.3 Boundary Scan Register (SDBSR)....................................................................... 746
25.3.4 ID Code Register (SDIDR) .................................................................................. 754
25.4 Operation........................................................................................................................... 755
25.4.1 TAP Controller State Transitions......................................................................... 755
25.4.2 H-UDI Reset ........................................................................................................ 755
25.5 Boundary Scan .................................................................................................................. 756
25.5.1 Supported Instructions ......................................................................................... 756
25.5.2 Notes .................................................................................................................... 757
25.6 Usage Notes ...................................................................................................................... 758
Section 26 Clock Pulse Generator
26.1 Oscillator........................................................................................................................... 762
26.1.1 Connecting a Crystal Oscillator ........................................................................... 762
26.1.2 External Clock Input Method............................................................................... 763
26.2 Duty Correction Circuit..................................................................................................... 765
26.3 Medium-Speed Clock Divider .......................................................................................... 766
26.4 Bus Master Clock Select Circuit ....................................................................................... 766
26.5 Subclock Input Circuit ...................................................................................................... 766
26.6 Waveform Forming Circuit............................................................................................... 767
26.7 Clock Select Circuit .......................................................................................................... 767
26.8 PLL Circuit ....................................................................................................................... 767
26.9 Usage Notes ...................................................................................................................... 768
26.9.1 Note on Resonator................................................................................................ 768
26.9.2 Notes on Board Design ........................................................................................ 768
26.9.3 Processing for X1 and X2 Pins ............................................................................ 769
Rev. 3.00 Jan 25, 2006 page xxxii of lii
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