Table 19.5 Card States In Which Command Sequence Is Halted - Renesas H8S/2158 User Manual

Section 19 Multimedia Card Interface (MCIF)
Bit Bit Name
4 DATAEN
3 to —
0
The command sequence on the MMC side may be halted according to the status of MMC. Table
19.5 shows the MMC states in which the command sequence is halted. In this case, the command
sequence should be aborted by setting the CMDOFF bit to 1 on the MCIF side as required.

Table 19.5 Card States in which Command Sequence Is Halted

Operating Mode
MMC mode Command response
Data status
SPI mode Command response
Data response
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REJ09B0286-0300
Initial Value R/W
0 R/W
All 0 R/(W)
Error Status
When the error detection bit in the card status (32 bits) in the
command response transmitted by the MMC is set.
When the error detection bit in the CRC status (3 bits) to be
transmitted from the MMC while block data is transmitted to
the MMC is set.
When the error detection bit in the card status (8 bits) in the
command response transmitted by the MMC is set.
When the error detection bit in the data response (8 bits) to
be transmitted from the MMC while block data is transmitted
to the MMC is set.
Description
Data Enable
Read as 1 during data transfer period after 1 is
written. Otherwise, read as 0. Starts write data
transmission by a command with write data.
Resumes transfer clock output and write data
transmission when the transfer clock is halted
according to FIFO empty or termination of one
block writing in multiblock write.
Write enable period:
•
After transmission of a command with write
data
•
While transfer clock is halted according to
FIFO empty
•
When one block writing in multiblock write
is terminated
0: Operation is not affected.
1: Starts or resumes transfer clock output and
write data transmission.
Reserved
The initial value should not be changed.