Operation Using Dtc - Renesas H8S/2158 User Manual

16-bit single-chip microcomputer h8s family/h8s/2100 series
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Section 17 I
C Bus Interface (IIC)
17.5.7

Operation Using DTC

This LSI provides the DTC to allow continuous data transfer. The DTC is activated when the
IRTR flag is set to 1, which is one of the two interrupt flags (IRTR and IRIC). When the ACKE
bit is 0, the ICDRE, IRIC, and IRTR flags are set at the end of data transmission regardless of the
acknowledge bit value. When the ACKE bit is 1, the ICDRE, IRIC, and IRTR flags are set if data
transmission is completed with the acknowledge bit value of 0, and when the ACKE bit is 1, only
the IRIC flag is set if data transmission is completed with the acknowledge bit value of 1.
When initiated, the DTC transfers specified number of bytes, and then clears the ICDRE, IRIC,
and IRTR flags to 0. Therefore, no interrupt is generated during continuous data transfer; however,
if data transmission is completed with the acknowledge bit value of 1 when the ACKE bit is 1, the
DTC is not activated, thus allowing an interrupt to be generated if enabled.
The acknowledge bit may indicate specific events such as completion of receive data processing
for some receiving devices, and for other receiving devices, the acknowledge bit may be held to 1,
indicating no specific events.
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The I
C bus format provides selection of the slave device and transfer direction by means of the
slave address and the R/W bit, and confirmation of reception and display of the last frame with the
acknowledge bit. Therefore, continuous data transfer using the DTC must be carried out in
conjunction with CPU processing by means of interrupts.
For transfer operations by the operation reservation adapter, a stop condition is automatically
issued when transfer of the number of transfer data bytes set by the DTC ends in master mode.
Table 17.8 shows some examples of processing using the DTC. Table 17.9 shows some examples
of operation reservation adapter processing using the DTC. These examples assume that the
number of transfer data bytes is known in slave mode.
Rev. 3.00 Jan 25, 2006 page 531 of 872
REJ09B0286-0300

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