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Start transmission
Read TDRE flag in SSR
Write transmit data to TDR and
set MPBT bit in SSR
Clear TDRE flag to 0
All data transmitted?
Read TEND flag in SSR
Break output?
Clear DR to 0 and set DDR to 1
Clear TE bit in SCR to 0
Figure 16.14 Sample Multiprocessor Serial Transmission Flowchart
16.5.2
Multiprocessor Serial Data Reception
Figure 16.16 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in
SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data
Section 16 Serial Communication Interface (SCI, IrDA, and CRC)
Initialization
No
TDRE = 1
Yes
No
Yes
No
TEND = 1
Yes
No
Yes
<End>
[1] SCI initialization:
[1]
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, a
frame of 1s is output, and
[2]
transmission is enabled.
[2] SCI status check and transmit
data write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR. Set the
MPBT bit in SSR to 0 or 1.
Finally, clear the TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission,
be sure to read 1 from the TDRE
[3]
flag to confirm that writing is
possible, then write data to TDR,
and then clear the TDRE flag to 0.
However, the TDRE flag is
checked and cleared
automatically when the DTC is
initiated by a transmit data empty
interrupt (TXI) request and writes
data to TDR.
[4] Break output at the end of serial
transmission:
To output a break in serial
[4]
transmission, set port DDR to 1,
clear DR to 0, and then clear the
TE bit in SCR to 0.
Rev. 3.00 Jan 25, 2006 page 433 of 872
REJ09B0286-0300
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