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CPU must read, interpret and execute a command from the FIFO. The slave CPU must process the
remaining transactions of a control transfer using FIFOs.
When the SETICNT bit is set to 1, the FIFO for EP0S is used and the SETUPF flag is set only
when a GetDescriptor, SetDescriptor, or device class specific command is received.
An interrupt transfer is comprised of a single IN or OUT transaction. The slave CPU must process
an interrupt transfer using FIFOs.
A bulk transfer is comprised of a single IN or OUT transaction. Transfer data is directly
transferred between on-chip RAM and USB modules by the RFU.
As described above, the USB module performs communication processing using both the USB
function core and slave CPU as required. Table 18.4 shows the USB function core and slave CPU
functions and the registers, flags, and bits used for interface.
Table 18.4 USB Function Core and Slave CPU Functions
No. Function
Analog ↔ digital conversion of the USDP/USDM
1
signal
Serial ↔ parallel conversion/ bit staffing, PID
2
check/addition, CRC check/addition
3
Token packet check/SETUP notification to the slave
CPU
4
Handshake packet check/generation
DATA0/1 PID toggle, FIFO rewind, ACK/NAC
detection/return
ACK handshake detection, notification to the slave
CPU/ACK handshake return
Data error detection, notification to the slave
CPU/NAK handshake return
STALL handshake return
5
Data packet reception/generation/transfer between the
slave CPU
6
USB command interpretation and execution
Section 18 Universal Serial Bus Interface (USB)
Operating
Hardware
Port unit
USB function
core
USB function
core
USB function
core
USB function
core
USB function
core
USB function
core, slave
CPU
Rev. 3.00 Jan 25, 2006 page 603 of 872
Related Registers,
Flags, and Bits
—
—
SETUPF, TS, EPTS,
TF, EPTF
FVSR, EPTE, RFU
TS, EPTS
TF, EPTF
EPSTL
FIFO, RFU
FIFO, RFU
REJ09B0286-0300
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