Section 12 16-Bit Free-Running Timer (FRT)
12.5
Operation Timing
12.5.1
FRC Increment Timing
Figure 12.3 shows the FRC increment timing with an internal clock source. Figure 12.4 shows the
increment timing with an external clock source. The pulse width of the external clock signal must
be at least 1.5 system clocks (φ). The counter will not increment correctly if the pulse width is
shorter than 1.5 system clocks (φ).
φ
Internal clock
FRC input
clock
FRC
Figure 12.3 Increment Timing with Internal Clock Source
φ
External clock
input pin
FRC input
clock
FRC
Figure 12.4 Increment Timing with External Clock Source
Rev. 3.00 Jan 25, 2006 page 300 of 872
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N – 1
N
N
N + 1
N + 1