16.10.3 Mark State And Break Detection; Receive Error Flags And Transmit Operations (Clocked Synchronous Mode Only); 16.10.5 Relation Between Writing To Tdr And Tdre Flag; 16.10.6 Restrictions On Using Dtc Or Rfu - Renesas H8S/2158 User Manual

Section 16 Serial Communication Interface (SCI, IrDA, and CRC)

16.10.3 Mark State and Break Detection

When the TE bit in SCR is 0, the TxD pin is used as an I/O port whose direction (input or output)
and level are determined by DR and DDR of the port. This can be used to set the TxD pin to mark
state (high level) or send a break during serial data transmission. To maintain the communication
line at mark state until TE is set to 1, set both DDR and DR to 1. Since the TE bit is cleared to 0 at
this point, the TxD pin becomes an I/O port, and 1 is output from the TxD pin. To send a break
during serial transmission, first set DDR to 1 and DR to 0, and then clear the TE bit to 0. When the
TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the
TxD pin becomes an I/O port, and 0 is output from the TxD pin.

16.10.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)

Transmission cannot be started when a receive error flag (ORER, FER, or RER) in SSR is set to 1,
even if the TDRE flag in SSR is cleared to 0. Be sure to clear the receive error flags to 0 before
starting transmission. Note also that the receive error flags cannot be cleared to 0 even if the RE
bit in SCR is cleared to 0.

16.10.5 Relation between Writing to TDR and TDRE Flag

Data can be written to TDR irrespective of the TDRE flag status in SSR. However, if the new data
is written to TDR when the TDRE flag is 0, that is, when the previous data has not been
transferred to TSR yet, the previous data in TDR is lost. Be sure to write transmit data to TDR
after verifying that the TDRE flag is set to 1.

16.10.6 Restrictions on Using DTC or RFU

When the external clock source is used as a synchronization clock, update TDR by the DTC or
RFU and wait for at least five φ clock cycles before allowing the transmit clock to be input. If the
transmit clock is input within four clock cycles after TDR modification, the SCI may malfunction
(figure 16.38).
When using the DTC or RFU to read RDR, be sure to set the receive end interrupt source (RXI) as
a DTC or RFU activation source.
Rev. 3.00 Jan 25, 2006 page 462 of 872
REJ09B0286-0300