I 2 C Bus Data Register (Icdr) - Renesas H8S/2158 User Manual

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• I
C bus data register (ICDR)
• Slave address register (SAR)
• Second slave address register (SARX)
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• I
C bus mode register (ICMR)
• I 2
C bus control register (ICCR)
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• I
C bus status register (ICSR)
• IIC operation reservation adapter control register (ICCRX)
• IIC operation reservation adapter status register A (ICSRA)
• IIC operation reservation adapter status register B (ICSRB)
• IIC operation reservation adapter status register C (ICSRC)
• IIC operation reservation adapter data register (ICDRX)
• IIC data shift register (ICDRS)
• IIC operation reservation adapter count register (ICCNT)
• IIC operation reservation adapter command register (ICCMD)
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17.3.1 I C Bus Data Register (ICDR)
ICDR is an 8-bit readable/writable register that is used as a transmit data register when
transmitting and a receive data register when receiving. ICDR is divided internally into a shift
register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). Data transfers among the
three registers are performed automatically in accordance with changes in the bus state, and they
affect the status of internal flags such as ICDRE and ICDRF. When ICDRE is 1 and the transmit
buffer is empty, ICDRE shows that the next transmit data can be written from the CPU. When
ICDRF is 1, it shows that valid receive data is stored in the receive buffer.
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If I C is in transmit mode and the next transmit data is in the transmit buffer (the ICDRE flag is 0)
after successful transmission/reception of one frame of data using the shift register, data is
transferred automatically from the transmit buffer to the shift register. If I
and no previous data remains in the receive buffer (the ICDRF flag is 0), data is transferred
automatically from the shift register to the receive buffer. Note however that no data is transferred
from the transmit buffer to the shift register in receive mode, and from the shift register to the
receive buffer in transmit mode. If ICDR is read from in transmit mode, data in the receive buffer
can be read but data in the shift register cannot. Always set I
from ICDR.
If the number of bits in a frame, excluding the acknowledge bit, is less than eight, transmit data
and receive data are stored differently. Transmit data should be written justified toward the MSB
side when MLS = 0 in ICMR, and toward the LSB side when MLS = 1. Receive data bits should
be read from the LSB side when MLS = 0, and from the MSB side when MLS = 1.
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Section 17 I C Bus Interface (IIC)
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C is in receive mode
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C to receive mode before reading
Rev. 3.00 Jan 25, 2006 page 477 of 872
REJ09B0286-0300