Table of Contents
Advertisement
Interrupt Acceptance Control and 3-Level Control: In interrupt control modes 0 and 1,
interrupt acceptance control and 3-level mask control is performed by means of the I and UI bits in
CCR and ICR (control level).
Table 5.5 shows the interrupts that can be accepted in each interrupt control mode.
Table 5.5
Interrupts Acceptable in Each Interrupt Control Mode
Interrupt
Control Mode
I Bit
0
0
1
1
0
1
Legend:
: Don't care
Note:
* Interrupt control level 1 has priority.
Default Priority Determination: The priority is determined for the selected interrupt, and a
vector number is generated.
If the same value is set for ICR, acceptance of multiple interrupts is enabled, and so only the
interrupt source with the highest priority according to the preset default priorities is selected and
has a vector number generated.
Interrupt sources with a lower priority than the accepted interrupt source are held pending.
Table 5.6 shows operations and control signal functions in each interrupt control mode.
NMI, Address
UI Bit
Break
O
O
O
0
O
1
O
Section 5 Interrupt Controller
KIN, WUE,
DTI
Peripheral Module Interrupt
O
O (All interrupts)
X
X
O
O (All interrupts)
X
O (Interrupts with ICR = 1)
X
X
Rev. 3.00 Jan 25, 2006 page 91 of 872
REJ09B0286-0300
Advertisement
Table of Contents
