Renesas H8S/2158 User Manual page 615

16-bit single-chip microcomputer h8s family/h8s/2100 series
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Section 18 Universal Serial Bus Interface (USB)
In host input transfer, FVSR is decremented by the number of bytes to be written if the slave CPU
writes to EPDR and sets the EPTE bit in PTTER0; FVSR is incremented by the number of bytes
to be read if the USB function core reads the FIFO and an ACK handshake is received from the
host.
In host output transfer, the FVSR is incremented by the number of bytes to be written if the USB
function core writes to the FIFO and sends an ACK handshake; FVSR is decremented by 1 if the
slave CPU reads the EPDR.
In certain situations, data must be re-transferred if a transfer error occurs. In this case, the FVSR is
not modified and the FIFO of the channel to be re-transferred will be re-wound.
In the USB protocol, the DATA0 and DATA1 packets are transmitted or received alternatively
during data transfer for each endpoint. Accordingly, the success of the data transfer can be
checked by the DATA0 and DATA1 packet toggles. If the DATA0 or DATA1 packet toggle is not
performed correctly, the USB function core stops the transaction processing and the FVSR value
does not change.
FVSR is a 2-byte register but can indicate the FIFO status only by using the lower byte, since the
FIFOs used in this LSI are 8 bytes, 16 bytes or 32 bytes. Therefore, only the lower byte of FSVR
must be read.
The upper byte of FSVR cannot be accessed directly. The upper byte of FSVR is sent to the
temporary register when the lower byte of FSVR is read and the contents of the temporary register
can be read when the upper byte of FSVR is read. If FSVR is read by word access, the contents of
the upper byte indicates the value when the lower byte has been read out.
FVSR0S, FVSR0O, and FVSR0I are automatically specified as H'0000, H'0000, and H'0010,
respectively when a SETUP token has been received.
FVSR is initialized by a system reset or function software reset (see section 18.3.16, USB Control
Registers 0 and 1 (USBCR0, USBCR1)) according to the transfer direction and the FIFO size
specified by EPDIR0 and EPSZR1.
Rev. 3.00 Jan 25, 2006 page 561 of 872
REJ09B0286-0300

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