Usb Interrupt Enable Registers 0 And 1 (Usbier0, Usbier1) - Renesas H8S/2158 User Manual

Bit Bit Name Initial Value R/W
7, 6 — All 0
5 EP4TE 0
4 EP3TE 0
3 EP2TE 0
2 EP1TE 0
1 EP0ITE 0
0 — 0
Note: * Only 1 can be written.
18.3.7

USB Interrupt Enable Registers 0 and 1 (USBIER0, USBIER1)

USBIER0 and USBIER1 provide interrupt enable bits that allow interrupt requests from the USB
function core to the slave CPU.
Section 18 Universal Serial Bus Interface (USB)
Description
R Reserved
These bits are always read as 0 and cannot be
modified.
R/(W) * Endpoint 4 Packet Transmission Enable
Prepares the transmission of RAM-FIFO data for
endpoint 4
0: Normal read value.
1: Prepares the transmission of RAM-FIFO data for
endpoint 4. The EP4TE bit must be set 1 for each
IN transfer in one transaction.
R/(W) * Endpoint 3 Packet Transmission Enable
Updates FVSR3 for endpoint 3
0: Normal read value.
1: Updates FVSR3 in endpoint 3-specific FIFO.
R/(W) * Endpoint 2 Packet Transmission Enable
Modifies FVSR2 for endpoint 2 if the EP2DIR bit is set
to 1.
0: Normal read value.
1: Updates FVSR2 in endpoint 2-specific FIFO.
R/(W) * Endpoint 1 Packet Transmission Enable
Updates FVSR2 for endpoint 1.
0: Normal read value.
1: Updates FVSR1 in endpoint 1-specific FIFO.
R/(W) * Endpoint 1 Packet Transmission Enable
Updates FVSR0I for endpoint 0.
0: Normal read value.
1: Updates FVSR0I in endpoint 0-specific FIFO.
R Reserved
This bit is always read as 0 and cannot be modified.
Rev. 3.00 Jan 25, 2006 page 565 of 872
REJ09B0286-0300