Renesas H8S/2158 User Manual page 540

2
Section 17 I C Bus Interface (IIC)
Bit Bit Name Initial Value R/W
5 MST 0
4 TRS 0
Rev. 3.00 Jan 25, 2006 page 486 of 872
REJ09B0286-0300
Description
R/W Master/Slave Select
R/W Transmit/Receive Select
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
Both these bits will be cleared by hardware when they
lose in a bus conflict in master mode of the I
format. In slave receive mode, the R/W bit in the first
frame immediately after the start condition automatically
sets these bits in receive mode or transmit mode by
hardware. The settings can be made again for the bits
that were set/cleared by hardware, by reading these bits.
When the TRS bit is intended to change during a transfer,
the bit will not be switched until data transfer ends.
[MST clearing conditions]
1. When 0 is written by software
2. When lost in bus conflict in I
mode
[MST setting conditions]
1. When 1 is written by software (for MST clearing
condition 1)
2. When 1 is written in MST after reading MST = 0 (for
MST clearing condition 2)
[TRS clearing conditions]
1. When 0 is written by software (except for TRS setting
condition 3)
2. When 0 is written in TRS after reading TRS = 1 (for
TRS setting condition 3)
3. When lost in bus conflict in I
mode
[TRS setting conditions]
1. When 1 is written by software (except for TRS
clearing condition 3)
2. When 1 is written in TRS after reading TRS = 0 (for
TRS clearing condition 3)
3. When 1 is received for the R/W bit value of the first
2
frame in I
2
C bus format master
2
C bus format master
C bus format slave mode
2
C bus