Basic Operation Timing; Figure 6.14 Access Timing Example In Burst Rom Space (Ast = Brsts1 = 1) - Renesas H8S/2158 User Manual

Section 6 Bus Controller
6.6.1

Basic Operation Timing

The number of access states in the initial cycle (full access) of the burst ROM interface is
determined by the AST bit in WSCR. When the AST bit is set to 1, wait states can be inserted. 1
or 2 states can be selected for burst access according to the setting of the BRSTS1 bit in BCR.
Wait states cannot be inserted in a burst cycle. Burst accesses of a maximum four words is
performed when the BRSTS0 bit in BCR is cleared to 0, and burst accesses of a maximum eight
words is performed when the BRSTS0 bit in BCR is set to 1.
The basic access timing for the burst ROM space is shown in figures 6.14 and 6.15.
Full access Burst access
T T T T T T T
1 2 3 1 2 1 2
φ
Address bus
Only lower address changes
AS/IOS
(IOSE = 0)
RD
Data bus
Read data Read data Read data

Figure 6.14 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 1)

Rev. 3.00 Jan 25, 2006 page 135 of 872
REJ09B0286-0300